Name
Abstract | ||
|---|---|---|
This profile is important because it matches the signal arrival time profile of the reduced partial products in a parallel multiplier before they are summed in the final adder.In this paper we present a design strategy specific to arrival time profiles generated by partial product reduction trees constructed by optimal application of the Three Dimensional Method presented by Oklobdzija, Villeger, and Liu and subsequently analyzed by Martel, Oklobdzija, Ravi, and Stelling. This strategy can be used to obtain adders for any arrival time profile that matches the above form, as well as a broad class of arrival time profiles where even greater variation in the input times is allowed.Finally, we show that our designs significantly out-perform the standard adder designs for the uniform signal arrival profile, yielding faster adders that (for these profiles) are also simpler and use fewer gates. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1007/BF00929625 | VLSI Signal Processing |
Keywords | Field | DocType |
Full Adder,Computer Arithmetic,Optimal Hybrid,Input Delay,Parallel Multiplier | Adder,Real-time computing,Multiplier (economics),Time profile,Mathematics,Partial product reduction,Three dimensional method | Journal |
Volume | Issue | ISSN |
14 | 3 | 0922-5773 |
Citations | PageRank | References |
21 | 2.36 | 8 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Paul F. Stelling | 1 | 33 | 3.86 |
| Vojin G. Oklobdzija | 2 | 806 | 137.25 |