Name
Title | ||
|---|---|---|
Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement. |
Year | Venue | Keywords |
|---|---|---|
1995 | IEICE Transactions | retiming,logic synthesis |
Field | DocType | Volume |
Logic synthesis,Testability,Retiming,Test synthesis,Sequential logic,Computer science,Parallel computing | Journal | 78-D |
Issue | Citations | PageRank |
7 | 0 | 0.34 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hiroyuki Yotsuyanagi | 1 | 70 | 19.04 |
| Seiji Kajihara | 2 | 989 | 73.60 |
| Kozo Kinoshita | 3 | 756 | 118.08 |