Paper Info
Title
An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan Chains
Abstract
In this paper, a Software-Based Diagnosis (SBD) procedure suitable for SoCs is proposed to tackle the diagnosis of transition-delay faults. The illustrated methodology takes advantage of an initial Software-Based Self-Test (SBST) test set and of the scan-chains included in the final SoC design release. In principle, the proposed methodology consists in partitioning the considered SBST test set in several slices, and then proceeding to the evaluation of the diagnostic ability owned by each slice with the aim of discarding diagnosis-ineffective test programs portions. The proposed methodology is aimed to provide precise feedback to the failure analysis process focusing the systematic timing failures characteristic of new technologies. Experimental results show the effectiveness and feasibility of the proposed approach on a suitable SoC test vehicle including an 8-bit microcontroller, 4 SRAM memories and an arithmetic core, manufactured by STMicroelectronics, whose purpose is to provide precise information to the failure analysis process. The reached diagnostic resolution is up to the 99.75%, compared to the 93.14% guaranteed by the original SBST procedure.
Year
DOI
Venue
2007
10.1109/DFT.2007.47
DFT
Keywords
Field
DocType
system on chip,failure analysis,soc
System on a chip,Computer science,Automatic testing,Static random-access memory,Electronic engineering,Real-time computing,Software,Microcontroller,Reliability engineering,Built-in self-test,Test set,Embedded system
Conference
ISSN
ISBN
Citations 
1550-5774
0-7695-2885-6
1
PageRank 
References 
Authors
0.35
22
7
Name
Order
Citations
PageRank
Lagos-Benites, J.111.03
Davide Appello2378.48
Paolo Bernardi324430.63
M. Grosso410911.39
Danilo Ravotto5334.40
Edgar E. Sánchez680.98
M. Sonza Reorda71099114.76