Name
Abstract | ||
|---|---|---|
Future mobile and wireless communication networks require flexible modem architectures to support seamless services between different network standards. Hence, a common hardware platform that can support multiple protocols implemented or controlled by software, generally referred to as software defined radio (SDR), is essential. This paper presents a family of dynamically reconfigurable application-specific instruction-set processors (ASIPs) for channel coding in wireless communication systems. As a weakly programmable intellectual property (IP) core, it can implement trellis-based channel decoding in a SDR environment. It features binary convolutional decoding, and turbo decoding for binary as well as duobinary turbo codes for all current and upcoming standards. The ASIP consists of a specialized pipeline with 15 stages and a dedicated communication and memory infrastructure. Logic synthesis revealed a maximum clock frequency of 400 MHz and an area of 0.11 mm2 for the processor's logic using a low power 65-nm technology. Memories require another 0.31 mm2. Simulation results for Viterbi and turbo decoding demonstrate maximum throughput of 196 and 34 Mb/s, respectively. The ASIP hence outperforms state-of-the-art decoder architectures targeting software defined radio by at least a factor of three while consuming only 60 % or less of the logic area. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TVLSI.2008.2002428 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
software defined radio,software radio,pipelines,viterbi algorithm,turbo code,convolutional code,viterbi decoding,logic synthesis,convolutional codes,computer architecture,intellectual property,turbo codes,decoding,channel coding,viterbi,application specific instruction set processor,wireless communication,low power electronics | Logic synthesis,Wireless,Convolutional code,Software-defined radio,Computer science,Turbo code,Electronic engineering,Real-time computing,Viterbi decoder,Decoding methods,Viterbi algorithm,Embedded system | Journal |
Volume | Issue | ISSN |
16 | 10 | 1063-8210 |
Citations | PageRank | References |
28 | 1.31 | 18 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Timo Vogt | 1 | 77 | 8.09 |
| Norbert Wehn | 2 | 1165 | 137.17 |