Title
Low-Power Design Of Cml Driver For On-Chip Transmission-Lines Using Impedance-Unmatched Driver
Abstract
This paper proposes a design technique to reduce the power dissipation of CML driver for on-chip trans mission-lines. CML drivers can operate at higher frequency than conventional static CMOS logic drivers. On the other hand, the power dissipation is larger than that of CMOS static logic drivers. The proposed method reduces the power dissipation by using an impedance-unmatched driver instead of the conventional impedance-matched driver. Measurement results show that the proposed method reduces the power dissipation by 32% compared with a conventional design at 12.5 Gbps.
Year
DOI
Venue
2007
10.1093/ietele/e90-c.6.1274
IEICE TRANSACTIONS ON ELECTRONICS
Keywords
Field
DocType
on-chip signaling, current-mode logic
Transmission line,Dissipation,Impedance matching,CMOS,Electrical impedance,Electric power transmission,Electronic engineering,Engineering,Current-mode logic,Electrical engineering,Low-power electronics
Journal
Volume
Issue
ISSN
E90C
6
1745-1353
Citations 
PageRank 
References 
6
0.99
0
Authors
3
Name
Order
Citations
PageRank
Takeshi Kuboki1122.69
Akira Tsuchiya23610.08
Hidetoshi Onodera3455105.29