| Supply and Threshold Voltage Scaling for Minimum Energy Operation over aWide Operating Performance Region | 0 | 0.34 | 2021 |
| Tamper-Resistant Optical Logic Circuits Based on Integrated Nanophotonics | 0 | 0.34 | 2021 |
| CDF Distance Based Statistical Parameter Extraction Using Nonlinear Delay Variation Models | 0 | 0.34 | 2021 |
| A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits | 0 | 0.34 | 2021 |
| Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration | 0 | 0.34 | 2021 |
| A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation | 0 | 0.34 | 2021 |
| On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation | 0 | 0.34 | 2020 |
| An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics | 0 | 0.34 | 2020 |
| 33.3 Via-Switch FPGA - 65nm CMOS Implementation and Architecture Extension for Al Applications. | 0 | 0.34 | 2020 |
| A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias | 0 | 0.34 | 2020 |
| MCell - Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing. | 0 | 0.34 | 2020 |
| A Design Method Of A Cell-Based Amplifier For Body Bias Generation | 0 | 0.34 | 2019 |
| Impact Of On-Chip Inductor And Power-Delivery-Network Stacking On Signal And Power Integrity | 0 | 0.34 | 2019 |
| NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map | 3 | 0.44 | 2019 |
| An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing | 0 | 0.34 | 2018 |
| PVT2: process, voltage, temperature and time-dependent variability in scaled CMOS process | 0 | 0.34 | 2018 |
| Design Methodology For Variation Tolerant D-Flip-Flop Using Regression Analysis | 0 | 0.34 | 2018 |
| Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture. | 0 | 0.34 | 2018 |
| A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation | 0 | 0.34 | 2018 |
| Independent N-Well And P-Well Biasing For Minimum Leakage Energy Operation | 0 | 0.34 | 2018 |
| Performance Modeling of VIA-Switch FPGA for Device-Circuit-Architecture Co-Optimization | 0 | 0.34 | 2018 |
| A Minimum Energy Point Tracking Algorithm Based On Dynamic Voltage Scaling And Adaptive Body Biasing | 0 | 0.34 | 2017 |
| A Necessary And Sufficient Condition Of Supply And Threshold Voltages In Cmos Circuits For Minimum Energy Point Operation | 1 | 0.36 | 2017 |
| A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region. | 1 | 0.35 | 2016 |
| On-chip monitoring and compensation scheme with fine-grain body biasing for robust and energy-efficient operations | 0 | 0.34 | 2016 |
| 2016 ASP-DAC. | 0 | 0.34 | 2016 |
| Analytical Stability Modeling For Cmos Latches In Low Voltage Operation | 0 | 0.34 | 2016 |
| Minimum energy point tracking using combined dynamic voltage scaling and adaptive body biasing | 1 | 0.38 | 2016 |
| Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing | 0 | 0.34 | 2016 |
| A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking | 0 | 0.34 | 2015 |
| An impact of process variation on supply voltage dependence of logic path delay variation | 0 | 0.34 | 2015 |
| Energy reduction by built-in body biasing with single supply voltage operation | 4 | 0.47 | 2015 |
| Microarchitectural-level statistical timing models for near-threshold circuit design | 3 | 0.40 | 2015 |
| Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis | 0 | 0.34 | 2015 |
| Modeling of advanced devices. | 0 | 0.34 | 2014 |
| Computer simulation of radiation-induced clock-perturbation in phase-locked loop with analog behavioral model | 0 | 0.34 | 2014 |
| Characterization and compensation of performance variability using on-chip monitors | 3 | 0.48 | 2014 |
| Radiation-Hardened Pll With A Switchable Dual Modular Redundancy Structure | 0 | 0.34 | 2014 |
| On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator | 0 | 0.34 | 2014 |
| Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design And Its Irradiation Testing | 3 | 0.54 | 2014 |
| A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation | 7 | 0.76 | 2014 |
| Frequency-Independent Warning Detection Sequential for Dynamic Voltage and Frequency Scaling in ASICs | 3 | 0.45 | 2014 |
| Design methodology of process variation tolerant D-Flip-Flops for low voltage circuit operation | 0 | 0.34 | 2014 |
| A Radiation-Hard Redundant Flip-Flop To Suppress Multiple Cell Upset By Utilizing The Parasitic Bipolar Effect | 1 | 0.37 | 2013 |
| AMS verification in advanced technologies. | 0 | 0.34 | 2013 |
| Analysis and comparison of XOR cell structures for low voltage circuit design | 1 | 0.38 | 2013 |
| On-Chip Detection Of Process Shift And Process Spread For Post-Silicon Diagnosis And Model-Hardware Correlation | 3 | 0.63 | 2013 |
| A flexible structure of standard cell and its optimization method for near-threshold voltage operation | 0 | 0.34 | 2012 |
| Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors | 6 | 1.36 | 2011 |
| A 65nm flip-flop array to measure soft error resiliency against high-energy neutron and alpha particles | 2 | 0.49 | 2011 |
