Name
Abstract | ||
|---|---|---|
We propose an algorithm, based on a framework of reconfigurable multiple scan-chains for a system-on-chip, to minimize test application time. For the framework, the control signal combination causes the computing time to increase exponentially. The algorithm we propose introduces a heuristic control signal selection method to solve this problem. We also minimize the test application time by using the balancing method to assign registers into multiple scan-chains. It could show significant reductions in test application times and computing times. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ISCAS.2005.1465968 | ISCAS (6) |
Keywords | Field | DocType |
integrated circuit testing,heuristic control signal selection,test application time minimization,control signal combination,system-on-chip,soc,balancing method,automatic testing,reconfigurable multiple scan-chains,minimisation,computer applications,multiplexing,algorithm design and analysis,registers,system testing,system on chip,system on a chip,design for testability | Design for testing,Heuristic,System on a chip,Algorithm design,Computer science,System testing,Electronic engineering,Minimisation (psychology),Computer Applications,Multiplexing | Conference |
ISSN | ISBN | Citations |
0271-4302 | 0-7803-8834-8 | 0 |
PageRank | References | Authors |
0.34 | 8 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jiann-Chyi Rau | 1 | 13 | 6.75 |
| Chih-lung Chien | 2 | 0 | 0.34 |
| Jia-shing Ma | 3 | 0 | 0.34 |