Paper Info
Title
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping
Abstract
In this paper, we propose an iterative area/performance tradeoff algorithm for look-up table (LUT)-based field programmable gate array (FPGA) technology mapping. First, it finds an area-optimized, performance-considered initial network by a modified area optimization technique. Then, an iterative algorithm consisting of several resynthesizing techniques is applied to trade the area for the performance in the network gracefully. Experimental results show that this approach can efficiently provide a complete set of mapping solutions from the area-optimized one to the performance-optimized one for the given design. Furthermore, these two extreme solutions produced by our algorithm outperform the results provided by most existing algorithms. Therefore, our algorithm is very useful for the timing-driven, LUT-based FPGA synthesis.
Year
DOI
Venue
2000
10.1109/92.863618
IEEE Trans. VLSI Syst.
Keywords
Field
DocType
lut-based fpga synthesis,existing algorithm,mapping solution,complete set,modified area optimization technique,performance tradeoff algorithm,iterative algorithm,lut-based fpga technology mapping,performance-considered initial network,technology mapping,iterative area,propagation delay,critical path analysis,look up table,indexing terms,routing,field programmable gate array,logic circuits,algorithm design and analysis,iterative methods,critical path,field programmable gate arrays
Lookup table,Logic gate,Algorithm design,Propagation delay,Computer science,Iterative method,Circuit design,Field-programmable gate array,Algorithm,Electronic engineering,Critical path method
Journal
Volume
Issue
ISSN
8
4
1063-8210
Citations 
PageRank 
References 
2
0.41
0
Authors
3
Name
Order
Citations
PageRank
Juinn-Dar Huang127027.42
Jing-Yang Jou268188.55
Wen-zen Shen39913.96