Name
Abstract | ||
|---|---|---|
Statistical analysis of bug discovery data is used in the software industry to check the quality of the testing process and estimate the reliability of the tested program. In this paper, we show that the same techniques are applicable to hardware design verification. We performed a study on two implementations of state-of-the-art PowerPC processors that shows that these techniques can provide quality information on the progress of verification and good predictions of the number of bugs left in the design and the future MTTF. |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1145/277044.277209 | DAC |
Keywords | Field | DocType |
software industry,microprocessor,validation,quality information,statistical analysis,21264,architecture,future mttf,good prediction,state-of-the-art powerpc processor,verification,pseudo-random,alpha,bug discovery data,testing process,coverage anaysis,hardware design verification,design reliability,pseudo random,computer bugs,investments,software reliability,formal verification,hardware,reliability,testing,computational modeling,process design | Mean time between failures,Data mining,Computer science,Software bug,Real-time computing,Software,Process design,Software quality,PowerPC,Reliability engineering,Automatic programming,Formal verification | Conference |
ISBN | Citations | PageRank |
0-89791-964-5 | 6 | 1.39 |
References | Authors | |
5 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yossi Malka | 1 | 137 | 28.86 |
| Avi Ziv | 2 | 465 | 72.49 |