Name
Abstract | ||
|---|---|---|
We present a new method to identify multi-site implications that can significantly increase the fault coverage of error-detecting hardware without increasing the area overhead. This method intelligently divides the input space about the functions of internal circuit sites and finds new valuable implications that can share gates in checker logic. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/VTS.2011.5783728 | 2011 IEEE 29TH VLSI TEST SYMPOSIUM (VTS) |
Keywords | Field | DocType |
logic circuits,process variation,logic gates,hardware,fault coverage,error detection,normal operator,benchmark testing,error rate | Logic gate,Fault coverage,Computer science,Real-time computing,Electronic engineering,Error detection and correction,Benchmark (computing) | Conference |
ISSN | Citations | PageRank |
1093-0167 | 7 | 0.51 |
References | Authors | |
12 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nuno Alves | 1 | 41 | 3.74 |
| Yiwen Shi | 2 | 23 | 2.44 |
| Jennifer Dworak | 3 | 7 | 0.51 |
| R. Iris Bahar | 4 | 878 | 84.31 |
| Kundan Nepal | 5 | 41 | 5.88 |