Paper Info
Title
A pipelined VLSI architecture for a list sphere decoder
Abstract
Since finding the nearest point in a lattice for multi-input multi-output (MIMO) channels is NP-hard, simplified algorithms such as a sphere decoder (SD) have been proposed. With simple modification of SD, a list sphere decoder (LSD), soft information can be extracted for channel decoding and iterative detection/decoding. However, generating such information increases the computational complexity for selecting a specific number of candidate lattice points. In this paper an efficient pipelined VLSI architecture for LSD is presented and its complexity is analyzed. The architecture is constructed with three pipeline stages, two stages for metric calculation units (MCU) and one stage for metric enumeration unit (MEU). It also has three storage units and list units for three successive input MIMO vectors. The pipeline can increase the operating clock frequency and keep one-node-per-cycle policy, so that the average throughput can enhance according to the increment of the clock frequency
Year
DOI
Venue
2006
10.1109/ISCAS.2006.1692606
ISCAS
Keywords
Field
DocType
np-hard,list sphere decoder,mimo channels,codecs,pipelined vlsi architecture,metric calculation units,channel coding,channel decoding,computational complexity,clocks,vlsi,integrated circuit design,iterative decoding,mimo systems,metric enumeration unit,pipelines,data mining,lattices,frequency,lattice points,np hard,very large scale integration,mimo,computer architecture
Computer science,Communication channel,MIMO,Electronic engineering,Throughput,Decoding methods,Very-large-scale integration,Clock rate,Codec,Computational complexity theory
Conference
ISSN
ISBN
Citations 
0271-4302
0-7803-9389-9
8
PageRank 
References 
Authors
0.84
2
3
Name
Order
Citations
PageRank
Jin Lee180.84
Sin-Chong Park28022.58
Sungchung Park35712.11