Paper Info
Title
A distributed interleaving scheme for efficient access to WideIO DRAM memory
Abstract
Achieving the main memory (DRAM) required bandwidth at acceptable power levels for current and future applications is a major challenge for System-on-Chip designers for mobile platforms. Three dimensional (3D) integration and 3D stacked DRAM memories promise to provide a significant boost in bandwidth at low power levels by exploiting multiple channels and wide data interfaces. In this paper, we address the problem of efficiently exploiting the multiple channels provided by standard (JEDEC's WIDE-IO) 3D-stacked memories, to extract maximal effective bandwidth and minimize latency for main memory access. We propose a new distributed interleaved access method that leverages the on-chip interconnect to simplify the design and implementation of the DRAM controller, without impacting performance compared to traditional centralized implementations. We perform experiments on realistic workload for a mobile communication and multimedia platform and show that our proposed distributed interleaving memory access method improves the overall throughput while minimally impacting the performance of latency sensitive communication flows.
Year
DOI
Venue
2012
10.1145/2380445.2380467
CODES+ISSS
Keywords
Field
DocType
maximal effective bandwidth,interleaved access method,dram memory,dram controller,interleaving memory access method,efficient access,wideio dram memory,required bandwidth,main memory access,acceptable power level,interleaving scheme,multiple channel,main memory,noc,interleaving
Dram,Registered memory,Access method,Computer science,Parallel computing,Real-time computing,Throughput,Memory controller,Interleaving,Memory rank,CAS latency,Embedded system
Conference
Citations 
PageRank 
References 
3
0.46
20
Authors
3
Name
Order
Citations
PageRank
Ciprian Seiculescu12199.26
Luca Benini2131161188.49
Giovanni De Micheli3102451018.13