3.5-D integration: A case study | 0 | 0.34 | 2013 |
Designing best effort networks-on-chip to meet hard latency constraints | 2 | 0.37 | 2013 |
CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers | 30 | 1.03 | 2012 |
A distributed interleaving scheme for efficient access to WideIO DRAM memory | 3 | 0.46 | 2012 |
A DRAM Centric NoC Architecture and Topology Design Approach | 3 | 0.38 | 2011 |
Networks on Chips: from research to products | 23 | 0.89 | 2010 |
A method to remove deadlocks in Networks-on-Chips with Wormhole flow control | 14 | 0.69 | 2010 |
Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands | 7 | 0.50 | 2010 |
SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips | 70 | 2.05 | 2009 |
Synthesis of networks on chips for 3D systems on chips | 50 | 1.61 | 2009 |
NoC topology synthesis for supporting shutdown of voltage islands in SoCs | 13 | 0.56 | 2009 |
A floorplan-aware interactive tool flow for NoC design and synthesis. | 4 | 0.38 | 2009 |