Name
Abstract | ||
|---|---|---|
Meeting timing constraint is one of the most important issues for modern design automation tools. This situation is exacerbated with the existence of process variation. Current high-level synthesis tools, performing task scheduling, resource allocation and binding, may result in unexpected performance discrepancy due to the ignorance of the impact of process variation, which requires a shift in the design paradigm, from today's deterministic design to statistical or probabilistic design. In this paper, we present a variation-aware performance yield-guaranteed high-level synthesis algorithm. The proposed approach integrates high-level synthesis and statistical static timing analysis into a simulated annealing engine to simultaneously explore solution space while meeting design objectives. Our results show that the area reduction is in the average of 14% when 95% performance yield is imposed with the same total completion time constraint. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1145/1233501.1233561 | ICCAD |
Keywords | Field | DocType |
high-level synthesis,deterministic design,design paradigm,probabilistic design,modern design automation tool,performance yield,process variation,high-level synthesis algorithm,current high-level synthesis tool,meeting design objective,guaranteeing performance yield,high level synthesis,electronic design automation,statistical analysis,resource allocation,design automation,formal methods,simulated annealing | Simulated annealing,Probabilistic design,Statistical static timing analysis,Design paradigm,Computer science,High-level synthesis,Real-time computing,Resource allocation,Electronic design automation,Design objective | Conference |
ISBN | Citations | PageRank |
1-59593-389-1 | 27 | 1.07 |
References | Authors | |
19 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| W-L. Hung | 1 | 157 | 8.06 |
| Xiaoxia Wu | 2 | 535 | 38.61 |
| Yuan Xie | 3 | 6430 | 407.00 |