Name
Abstract | ||
|---|---|---|
In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency prescalers are investigated. Based on this study a new low power and improved speed TSPC 2/3 prescaler is proposed which is silicon verified. Compared with the existing TSPC architectures the proposed 2/3 prescaler is capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V. This extremely low power consumption is achieved by radically decreasing the sizes of transistors, reducing the number of switching stages and blocking the power supply to one of the D flip-flops (DFF) during Divide-by-2 operation. A divide-by-32/33 dual modulus prescaler implemented with this 2/3 prescaler using a Chartered 0.18 µm CMOS technology is capable of operating up to 4.5 GHz with a power consumption of 1.4 mW. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/TCSI.2009.2016183 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
ultra low power,true single phase clock,extended true single phase,existing tspc,new low power,low power consumption,m cmos technology,power supply,power consumption,supply voltage,frequency prescalers,silicon,frequency synthesizer,sequential circuits,dual modulus prescaler,logic gates,digital circuits,cmos technology | Logic gate,Frequency divider,Dual-modulus prescaler,Voltage,CMOS,Electronic engineering,Frequency synthesizer,Transistor,Energy consumption,Electrical engineering,Mathematics | Journal |
Volume | Issue | ISSN |
57 | 1 | 1549-8328 |
Citations | PageRank | References |
19 | 1.81 | 9 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Manthena Vamshi Krishna | 1 | 20 | 2.21 |
| Manh Anh Do | 2 | 176 | 24.95 |
| Kiat Seng Yeo | 3 | 365 | 63.72 |
| Chirn Chye Boon | 4 | 136 | 26.81 |
| Wei Meng Lim | 5 | 108 | 20.32 |