Name
Abstract | ||
|---|---|---|
Numerous variations of configurable caches, having variable parameters like total size, line size, and associativity, have been proposed in commercial microprocessors in recent years. Tuning a configurable cache to a target application has been shown to reduce memory-access power by over 50%. However, searching the configuration space for the best configuration can require much time or power, even when using recent cache tuning heuristics. We sought to determine, for a particular domain of applications, the smallest subset of cache configurations that would still enable effective tuning. For a suite of 34 benchmarks and a cache with 18 possible configurations, we determine through an exhaustive search of all possible subsets, that only 3 or 4 candidate configurations are necessary to support tuning. We introduce a new heuristic, adapted from an efficient and effective heuristic developed for data mining, to quickly determine the best configurations for any sized subset, with near optimal results. We then consider a configurable cache with 17,640 possible configurations and improve our heuristic to include a pre-pruning step, yielding near optimal tuning results. We conclude that only 3 or 4 possible cache configurations are needed to offer a near optimal configuration for every benchmark in our suite - resulting in a 91% reduction in design space exploration time over a state-of-the-art cache tuning heuristic. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1145/1146909.1147085 | DAC |
Keywords | Field | DocType |
effective tuning,configurable cache,effective heuristic,fast cache tuning,optimal tuning result,best configuration,state-of-the-art cache,possible configuration,recent cache,cache configuration,possible cache configuration,computer architecture,integrated circuit design,data mining,algorithms,microcomputers,configuration space,exhaustive search | Cache-oblivious algorithm,Heuristic,Cache invalidation,Computer science,Cache,Parallel computing,Cache algorithms,Real-time computing,Cache coloring,Smart Cache,Design space exploration | Conference |
ISSN | ISBN | Citations |
0738-100X | 1-59593-381-6 | 13 |
PageRank | References | Authors |
0.60 | 10 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pablo Viana | 1 | 14 | 0.97 |
| Ann Gordon-Ross | 2 | 513 | 47.78 |
| Eamonn J. Keogh | 3 | 11859 | 645.93 |
| Edna Barros | 4 | 145 | 13.04 |
| Frank Vahid | 5 | 2688 | 218.00 |