Name
Abstract | ||
|---|---|---|
In this paper, two algorithms for layer assignment with the goal of yield enhancement are proposed. In the first, vias in an existing layout are moved in order to decrease its sensitivity to defects. A greedy algorithm for achieving this objective is presented. In the second, we formulate the layer assignment problem as a network bipartitioning problem. By applying the primal-dual algorithm (a variation of the Kernighan-Lin algorithm), the objective of critical area minimization can be achieved. These two methods are applied to a set of benchmark circuits to demonstrate their effectiveness |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/DFTVS.1995.476950 | DFT |
Keywords | Field | DocType |
yield enhancement,benchmark circuits,network routing,primal-dual algorithm,layer assignment problem,existing layout,circuit optimisation,kernighan-lin algorithm,defect sensitivity,circuit layout cad,greedy algorithm,layer assignment,network bipartitioning problem,benchmark circuit,vlsi,vias,integrated circuit yield,integrated circuit layout,critical area minimization,artificial intelligence,routing,greedy algorithms,very large scale integration,assignment problem,manufacturing | Integrated circuit layout,Mathematical optimization,Computer science,Network routing,Electronic engineering,Greedy algorithm,Assignment problem,Minification,Critical area,Electronic circuit,Very-large-scale integration | Conference |
ISSN | ISBN | Citations |
1550-5774 | 0-8186-7107-6 | 5 |
PageRank | References | Authors |
0.80 | 10 | 2 |