Title | ||
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Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment |
Abstract | ||
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This paper describes the early analysis and estimationfeatures currently implemented in the Berkeley EmulationEngine (BEE) system. BEE is an integrated rapid prototypingand design environment for communication and digitalsignal processing (DSP) systems, consisting of four multi-FPGA based processing units, each capable of emulating 10 million ASIC (Application Specific Integrated Circuits)equivalent gates at an overall system clock rate up to 60MHz. This translates to over 600 billion 16-bit additions(operations) per second on one unit. An integrated softwaredesign flow enables the users to specify the design using adata-flow diagram, then automatically generates both theFPGA implementation for real-time rapid prototyping anda cycle-accurate, bit-true, and functionally equivalent ASICimplementation. For system-level design, the BEE hardwareand software support rapid design turn-around and early performance analysis, without full synthesis or hardwaremapping, from the high-level design entry. A case study detailing a turbo-decoder explains how the processingcapability of the emulator can be utilized to verify a design using one billion input vectors with a speed-up factorexceeding 106 over equivalent software simulationmethods. |
Year | DOI | Venue |
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2003 | 10.1109/IWRSP.2003.1207042 | IEEE International Workshop on Rapid System Prototyping |
Keywords | Field | DocType |
equivalent gate,equivalent software simulationmethods,system-level design,high-level design entry,functionally equivalent,bee hardwareand software support,rapid design turn-around,billion 16-bit addition,integrated rapid prototypingand design,bee hardware emulation environment,real-time rapid prototyping anda,communication systems,rapid design,application specific integrated circuits,data flow diagram,hardware,virtual machines,digital signal processing,real time,high level design,emulation,engines,prototypes,software design,system level design,field programmable gate arrays,application specific integrated circuit,communication system,signal processing | High-level design,Computer architecture,Software design,Computer science,Electronic system-level design and verification,Field-programmable gate array,Application-specific integrated circuit,Real-time computing,Design flow,Emulation,Hardware emulation,Embedded system | Conference |
ISSN | ISBN | Citations |
1074-6005 | 0-7695-1743-1 | 24 |
PageRank | References | Authors |
6.78 | 4 | 7 |
Name | Order | Citations | PageRank |
---|---|---|---|
Chen Chang | 1 | 174 | 26.12 |
Kimmo Kuusilinna | 2 | 216 | 27.10 |
Brian Richards | 3 | 140 | 16.18 |
Allen Chen | 4 | 24 | 6.78 |
Nathan Chan | 5 | 46 | 17.31 |
Robert W. Brodersen | 6 | 1857 | 401.31 |
Borivoje Nikoliæ | 7 | 24 | 6.78 |