Name
Title | ||
|---|---|---|
Simulation And Modeling Of Substrate Noise Generation From Synchronous And Asynchronous Digital Logic Circuits |
Abstract | ||
|---|---|---|
An efficient methodology for simulating the substrate noise generated by complex synchronous and asynchronous digital logic circuits is presented. By simulating digital logic at the gate level, and precharacterizing the gates, the substrate noise generation can be predicted and used in a transistor level simulation of the sensitive analog blocks. This approach is shown to be accurate for both traditional CMOS logic and NULL Convention Logic (NCL) by correctly modeling critical gate characteristics. Simulations with different implementations of an 8051 processor core are in good agreement with measurements from a 0.25 mu m CMOS test chip. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/CICC.2007.4405860 | PROCEEDINGS OF THE IEEE 2007 CUSTOM INTEGRATED CIRCUITS CONFERENCE |
Keywords | Field | DocType |
substrate noise, synchronous, asynchronous, null conventional logic, simulation | Digital electronics,Logic gate,Pass transistor logic,Computer science,Electronic engineering,Resistor–transistor logic,Logic simulation,Logic level,Logic family,Asynchronous circuit | Conference |
Citations | PageRank | References |
1 | 0.35 | 9 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christopher Hanken | 1 | 3 | 1.08 |
| Jim Le | 2 | 3 | 1.08 |
| Terri S. Fiez | 3 | 167 | 47.25 |
| Kartikeya Mayaram | 4 | 349 | 58.50 |