Paper Info
Title
The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors
Abstract
This work is focused on accelerating upgrade misses in cc-NUMA multiprocessors. These misses are caused by store instructions for which a read-only copy of the line is found in the L2 cache. Upgrade misses require a message sent from the missing node to the directory, a directory lookup in order to find the set of sharers, invalidation messages being sent to the sharers and responses to the invalidations being sent back. Therefore, the penalty paid by these misses is not negligible, mainly if we consider that they account for a high percentage of the total miss rate. We propose the use of prediction as a means of providing cc-NUMA multiprocessors with a more efficient support for upgrade misses by directly invalidating sharersfrom the missing node. Our proposal comprises an effective prediction scheme achieving high hit rates as well as a coherence protocol extended to support the use of prediction. Our work is motivated by two key observations: first, upgrade misses present a repetitive behavior and, second, the total number of sharers being invalidated is small (one, in some cases). Using execution-driven simulations, we show that the use of prediction can significantly accelerateupgrade misses (latency reductions of more than 40% in some cases). These important improvements translate into speed-ups on application performance up to 14%. Finally, these results can be obtained including a predictor with a total size of less than 48 KB in every node.
Year
DOI
Venue
2002
10.1109/PACT.2002.1106014
IEEE PACT
Keywords
Field
DocType
efficient support,cc-numa multiprocessors,total number,missing node,high percentage,directory lookup,accelerating upgrade miss,high hit rate,effective prediction scheme,l2 cache,total size,predictive models,coherence,enumeration,out of order,hardware,acceleration,dictionary,prediction,embedded processor,instruction scheduling
Instruction scheduling,CPU cache,Directory,Latency (engineering),Computer science,Parallel computing,Upgrade,Real-time computing,Operating system
Conference
ISSN
ISBN
Citations 
1089-795X
0-7695-1620-3
25
PageRank 
References 
Authors
1.14
22
4
Name
Order
Citations
PageRank
M. E. Acacio141941.45
José González252635.85
J. M. García358858.90
José Duato43481294.85