Title
Limitations and challenges of computer-aided design technology for CMOS VLSI
Abstract
As manufacturing technology moves toward fundamental limits of silicon CMOS processing, the ability to reap the full potential of available transistors and interconnect is increasingly important. Design technology (DT) is concerned with the automated or semi-automated conception, synthesis, verification, and eventual testing of microelectronic systems. While manufacturing technology faces fundamental limits inherent in physical laws or material properties, design technology faces fundamental limitations inherent in the computational intractability of design optimizations and in the broad and unknown range of potential applications within various design processes. In this paper, we explore limitations to how design technology can enable the implementation of single-chip microelectronic systems that take full advantage of manufacturing technology with respect to such criteria as layout density performance, and power dissipation
Year
DOI
Venue
2001
10.1109/5.915378
Proceedings of the IEEE
Keywords
DocType
Volume
CMOS digital integrated circuits,VLSI,circuit CAD,circuit layout CAD,circuit optimisation,design for testability,high level synthesis,integrated circuit design,integrated circuit testing,mixed analogue-digital integrated circuits,timing,ASIC,CAD technology,CMOS VLSI,DFT,IC design process,Si,Si CMOS ICs,automated synthesis,computer-aided design technology,design optimizations,integrated circuit design process,layout density performance,power dissipation,single-chip microelectronic systems,testing,verification
Journal
89
Issue
ISSN
Citations 
3
0018-9219
31
PageRank 
References 
Authors
3.74
40
9
Name
Order
Citations
PageRank
Randal E. Bryant192041194.64
Kwang-Ting Cheng25755513.90
Andrew B. Kahng37582859.06
Kurt Keutzer45040801.67
Wojciech Maly51976352.57
Richard Newton6989.57
Lawrence Pileggi735831.47
Jan M. Rabaey847961049.96
Alberto L. Sangiovanni-Vincentelli9113851881.40