Name
Title | ||
|---|---|---|
Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs |
Year | Venue | Keywords |
|---|---|---|
2005 | PARCO | network on chip |
Field | DocType | Citations |
Computer architecture,Public records,Computer science,Parallel computing,Field-programmable gate array,Functional validation,Artificial intelligence | Conference | 3 |
PageRank | References | Authors |
0.54 | 12 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| J. B. Pérez-ramas | 1 | 3 | 0.54 |
| David Atienza | 2 | 2219 | 149.60 |
| M. Peón | 3 | 8 | 1.07 |
| Ivan Magan | 4 | 3 | 0.54 |
| Jose Manuel Mendias | 5 | 17 | 2.77 |
| Román Hermida | 6 | 89 | 15.34 |