Paper Info
Title
An Effective Decap Insertion Method Considering Power Supply Noise during Floorplanning
Abstract
As VLSI technology enters the nanometer era, the supply voltage is continually dropped. This condition helps to reduce the power dissipation, but make the power integrity problem become worse. Employing decoupling capacitances (decap) at floorplan stage has been a common approach to alleviate the supply noise problem. However, the decap budget is often overly estimated in previous researches. Besides the decap budget computation, the available floorplan space does not fully used in previous works. In one floorplan, it usually has many available spaces except the empty space that could be used to insert the decap without increasing the floorplan area. Therefore, our goal in this work is to develop a better model to calculate the required decap to solve the power supply noise problem of area-array based designs and to increase he usage of the available space in the floorplan to reduce the area overhead caused by decap insertion. The experimental results are encouraging. Compared with other approaches, our algorithm can reduce 52.6% decap budget on the MCNC benchmarks but still keep the power supply noise in the given constraint. The final floorplan areas with decap are also less than the numbers reported in previous papers.
Year
Venue
Keywords
2008
JOURNAL OF INFORMATION SCIENCE AND ENGINEERING
decoupling capacitance,floorplanning,physical design,power estimation,area-array architecture
Field
DocType
Volume
Computer science,Decoupling (cosmology),Voltage,Power integrity,Electronic engineering,Physical design,Very-large-scale integration,Bin packing problem,Computation,Floorplan,Distributed computing
Journal
24
Issue
ISSN
Citations 
1
1016-2364
0
PageRank 
References 
Authors
0.34
12
3
Name
Order
Citations
PageRank
Chao-Hung Lu1112.68
Hung-Ming Chen249359.19
Chien-Nan Jimmy Liu39727.07