Name
Abstract | ||
|---|---|---|
In this paper we present a new approach for generating high-speed optimized event-driven instruction set level simulators for adaptive massively parallel processor architectures. The simulator generator is part of a methodology for the systematic mapping, evaluation, and exploration of massively parallel processor architectures that are designed for special purpose applications in the world of embedded computers. The generation of high-speed cycle-accurate simulators is of utmost importance here, because they are directly used both for parallel processor architecture debugging and evaluation purposes, as well as during time-consuming architecture/compiler co-exploration. We developed a modeling environment which automatically generates a C++ simulation model either from a graphical input or directly from an XML-based architecture description. Here, we focus on the underlying event-driven simulation model and present our modeling environment, in particular the features of the graphical parallel processor architecture editor and the automatic instruction set level simulator generator. Finally, in a case-study, we demonstrate the pertinence of our approach by simulating different processor arrays. The superior performance of the generated simulators compared to existing simulators and simulator generation approaches is shown. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1145/1269843.1269854 | SCOPES |
Keywords | Field | DocType |
parallel processor architecture debugging,time-consuming architecture,graphical parallel processor architecture,simulator generator,parallel processor architecture,modeling environment,different processor array,high-speed cycle-accurate simulator,xml-based architecture description,set level simulator,efficient event-driven simulation,embedded computing,simulation model,processor architecture,simulation,modeling | Application-specific instruction-set processor,Computer architecture,Computer architecture simulator,XML,Computer science,Massively parallel,Software architecture description,Instruction set,Parallel computing,Compiler,Real-time computing,Debugging | Conference |
Citations | PageRank | References |
5 | 0.45 | 14 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alexey Kupriyanov | 1 | 79 | 6.40 |
| Dmitrij Kissler | 2 | 78 | 7.30 |
| Frank Hannig | 3 | 595 | 75.66 |
| Jürgen Teich | 4 | 2886 | 273.54 |