Name
Abstract | ||
|---|---|---|
This paper introduces Embedded Deterministic Test (EDT) technology, which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The EDT architecture, the compression algorithm, design flow, experimental results, and silicon implementation are presented. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/TEST.2002.1041773 | ITC |
Keywords | Field | DocType |
silicon implementation,design flow,edt architecture,low-cost manufacturing test,compression algorithm,test time,magnitude reduction,test cost,test data volume,deterministic test,test coverage,manufacturing,vlsi,frequency,design for testability,atpg,dft,graphics,automatic test pattern generation,data compression | Design for testing,Code coverage,Automatic test pattern generation,Computer science,Electronic engineering,Design flow,Real-time computing,Test data,Data compression,Test compression,Very-large-scale integration,Reliability engineering | Conference |
ISSN | ISBN | Citations |
1089-3539 | 0-7803-7543-2 | 247 |
PageRank | References | Authors |
13.26 | 24 | 11 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Januz Rajki | 1 | 247 | 13.26 |
| Jerzy Tyzer | 2 | 247 | 13.26 |
| Mark Kassab | 3 | 654 | 48.74 |
| Nilanjan Mukherjee | 4 | 801 | 57.26 |
| Rob Thompson | 5 | 279 | 14.60 |
| Kun-Han Tsai | 6 | 600 | 40.79 |
| Andre Hertwig | 7 | 253 | 14.19 |
| Nagesh Tamarapalli | 8 | 772 | 58.83 |
| Grzegorz Mrugalski | 9 | 501 | 35.90 |
| Geir Eide | 10 | 247 | 13.94 |
| Jun Qian | 11 | 247 | 13.26 |