Name
Title | ||
|---|---|---|
Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning |
Abstract | ||
|---|---|---|
Hierarchical models from physical to system-level are proposed for architectural exploration of high-performance silicon systems to quantify the performance and cost trade offs for 2-D and 3-D IC implementations. We show that 3-D systems can reduce interconnect delay and energy by up to an order of magnitude over 2-D, with an increase of 20-30% in performance-per-watt for every doubling of stack height. Contrary to previous analysis, the improved energy efficiency is achievable at a favorable cost. The models are packaged as a standalone tool and can provide fast estimation of coarse-grain performance and cost limitations for a variety of processing systems to be used at the early chip-planning phase of the design cycle.
|
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ICCAD.2011.6105347 | ICCAD |
Keywords | DocType | ISSN |
cost limitation,design cycle,early-chip planning,3-d ic implementation,computational efficiency,cost trade offs,3-d silicon processor,early chip-planning phase,3-d system,favorable cost,architectural exploration,coarse-grain performance,improved energy efficiency,resistive ram,energy efficient,memristor,chip,silicon,hierarchical model | Conference | 1933-7760 |
ISBN | Citations | PageRank |
978-1-4577-1398-9 | 0 | 0.34 |
References | Authors | |
16 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Matthew Grange | 1 | 0 | 0.68 |
| Axel Jantsch | 2 | 1875 | 169.83 |
| Roshan Weerasekera | 3 | 166 | 13.61 |
| Dinesh Pamunuwa | 4 | 236 | 22.55 |