Name
Affiliation
Papers
AXEL JANTSCH
Royal Institute of Technology (KTH), Stockholm, Sweden
244
Collaborators
Citations 
PageRank 
318
1875
169.83
Referers 
Referees 
References 
3270
3809
2566
Search Limit
1001000
Title
Citations
PageRank
Year
Reliable Power Efficient Systems through Run-time Reconfiguration00.342022
Improving Deep Learning Based Anomaly Detection on Multivariate Time Series Through Separated Anomaly Scoring00.342022
MLComp: A Methodology for Machine Learning-based Performance Estimation and Adaptive Selection of Pareto-Optimal Compiler Optimization Sequences00.342021
Modular and Distributed Management of Many-Core SoCs00.342021
Model-Free Condition Monitoring With Confidence10.372019
Improved Machine Learning using Confidence.00.342019
Computer-aided Arrhythmia Diagnosis with Bio-signal Processing: A Survey of Trends and Techniques20.382019
Towards a Formal Model of Recursive Self-Reflection.00.342019
Efficient Design-for-Test Approach for Networks-on-Chip.10.352019
Guest Editorial: Special Issue on Self-Aware Systems on Chip.00.342018
Applicability Of Context-Aware Health Monitoring To Hydraulic Circuits00.342018
adBoost: Thermal Aware Performance Boosting Through Dark Silicon Patterning.10.342018
Smartdpm: Machine Learning-Based Dynamic Power Management For Multi-Core Microprocessors00.342018
Goal Formulation: Abstracting Dynamic Objectives for Efficient On-chip Resource Allocation10.362018
Self-Awareness in Systems on Chip - A Survey.40.522017
Empowering autonomy through self-awareness in MPSoCs00.342017
Can Dark Silicon Be Exploited to Prolong System Lifetime?00.342017
Self-awareness in remote health monitoring systems using wearable electronics.20.452017
Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient Applications.20.392017
Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era.90.512017
Optimizing the location of ECC protection in network-on-chip.00.342016
Fully digital write-in scheme for multi-bit memristive storage10.362016
Toward Smart Embedded Systems: A Self-aware System-on-Chip (SoC) Perspective.161.012016
Comprehensive Observation and its Role in Self-Awareness; An Emotion Recognition System Example.60.652016
A Routing-Level Solution for Fault Detection, Masking, and Tolerance in NoCs20.352015
MapPro: Proactive Runtime Mapping for Dynamic Workloads by Quantifying Ripple Effect of Applications on Networks-on-Chip130.622015
Building reliable systems-on-chip in nanoscale technologies00.342015
Self-Aware Cyber-Physical Systems-on-Chip30.422015
Performance analysis of homogeneous on-chip large-scale parallel computing architectures for data-parallel applications10.362015
Memristors' Potential for Multi-bit Storage and Pattern Learning20.392015
MultiCS: Circuit switched NoC with multiple sub-networks and sub-channels40.422015
Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach160.682015
Dark silicon aware power management for manycore systems under dynamic workloads50.472014
Rescuing healthy cores against disabled routers00.342014
Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips10.352014
A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource Allocation10.362014
Editorial introduction - Special issue on languages, models and model based design for embedded systems.00.342014
Parallel probe based dynamic connection setup in TDM NoCs60.502014
Efficient distributed memory management in a multi-core H.264 decoder on FPGA10.362013
Mathematical formalisms for performance evaluation of networks-on-chip210.782013
Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation.40.392012
Performance analysis of reconfiguration in adaptive real-time streaming applications50.522012
Architecture Support and Comparison of Three Memory Consistency Models in NoC Based Systems10.342012
Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning00.342011
Evaluation of deflection routing on various NoC topologies30.402011
Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks20.392011
Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems10.352011
3-D integration and the limits of silicon computation.00.342011
Cooperative Communication Based Barrier Synchronization In On-Chip Mesh Architectures30.462011
Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems30.412011
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