Reliable Power Efficient Systems through Run-time Reconfiguration | 0 | 0.34 | 2022 |
Improving Deep Learning Based Anomaly Detection on Multivariate Time Series Through Separated Anomaly Scoring | 0 | 0.34 | 2022 |
MLComp: A Methodology for Machine Learning-based Performance Estimation and Adaptive Selection of Pareto-Optimal Compiler Optimization Sequences | 0 | 0.34 | 2021 |
Modular and Distributed Management of Many-Core SoCs | 0 | 0.34 | 2021 |
Model-Free Condition Monitoring With Confidence | 1 | 0.37 | 2019 |
Improved Machine Learning using Confidence. | 0 | 0.34 | 2019 |
Computer-aided Arrhythmia Diagnosis with Bio-signal Processing: A Survey of Trends and Techniques | 2 | 0.38 | 2019 |
Towards a Formal Model of Recursive Self-Reflection. | 0 | 0.34 | 2019 |
Efficient Design-for-Test Approach for Networks-on-Chip. | 1 | 0.35 | 2019 |
Guest Editorial: Special Issue on Self-Aware Systems on Chip. | 0 | 0.34 | 2018 |
Applicability Of Context-Aware Health Monitoring To Hydraulic Circuits | 0 | 0.34 | 2018 |
adBoost: Thermal Aware Performance Boosting Through Dark Silicon Patterning. | 1 | 0.34 | 2018 |
Smartdpm: Machine Learning-Based Dynamic Power Management For Multi-Core Microprocessors | 0 | 0.34 | 2018 |
Goal Formulation: Abstracting Dynamic Objectives for Efficient On-chip Resource Allocation | 1 | 0.36 | 2018 |
Self-Awareness in Systems on Chip - A Survey. | 4 | 0.52 | 2017 |
Empowering autonomy through self-awareness in MPSoCs | 0 | 0.34 | 2017 |
Can Dark Silicon Be Exploited to Prolong System Lifetime? | 0 | 0.34 | 2017 |
Self-awareness in remote health monitoring systems using wearable electronics. | 2 | 0.45 | 2017 |
Accuracy-Aware Power Management for Many-Core Systems Running Error-Resilient Applications. | 2 | 0.39 | 2017 |
Reliability-Aware Runtime Power Management for Many-Core Systems in the Dark Silicon Era. | 9 | 0.51 | 2017 |
Optimizing the location of ECC protection in network-on-chip. | 0 | 0.34 | 2016 |
Fully digital write-in scheme for multi-bit memristive storage | 1 | 0.36 | 2016 |
Toward Smart Embedded Systems: A Self-aware System-on-Chip (SoC) Perspective. | 16 | 1.01 | 2016 |
Comprehensive Observation and its Role in Self-Awareness; An Emotion Recognition System Example. | 6 | 0.65 | 2016 |
A Routing-Level Solution for Fault Detection, Masking, and Tolerance in NoCs | 2 | 0.35 | 2015 |
MapPro: Proactive Runtime Mapping for Dynamic Workloads by Quantifying Ripple Effect of Applications on Networks-on-Chip | 13 | 0.62 | 2015 |
Building reliable systems-on-chip in nanoscale technologies | 0 | 0.34 | 2015 |
Self-Aware Cyber-Physical Systems-on-Chip | 3 | 0.42 | 2015 |
Performance analysis of homogeneous on-chip large-scale parallel computing architectures for data-parallel applications | 1 | 0.36 | 2015 |
Memristors' Potential for Multi-bit Storage and Pattern Learning | 2 | 0.39 | 2015 |
MultiCS: Circuit switched NoC with multiple sub-networks and sub-channels | 4 | 0.42 | 2015 |
Dynamic power management for many-core platforms in the dark silicon era: A multi-objective control approach | 16 | 0.68 | 2015 |
Dark silicon aware power management for manycore systems under dynamic workloads | 5 | 0.47 | 2014 |
Rescuing healthy cores against disabled routers | 0 | 0.34 | 2014 |
Performance and network power evaluation of tightly mixed SRAM NUCA for 3D Multi-core Network on Chips | 1 | 0.35 | 2014 |
A Fair and Maximal Allocator for Single-Cycle On-Chip Homogeneous Resource Allocation | 1 | 0.36 | 2014 |
Editorial introduction - Special issue on languages, models and model based design for embedded systems. | 0 | 0.34 | 2014 |
Parallel probe based dynamic connection setup in TDM NoCs | 6 | 0.50 | 2014 |
Efficient distributed memory management in a multi-core H.264 decoder on FPGA | 1 | 0.36 | 2013 |
Mathematical formalisms for performance evaluation of networks-on-chip | 21 | 0.78 | 2013 |
Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation. | 4 | 0.39 | 2012 |
Performance analysis of reconfiguration in adaptive real-time streaming applications | 5 | 0.52 | 2012 |
Architecture Support and Comparison of Three Memory Consistency Models in NoC Based Systems | 1 | 0.34 | 2012 |
Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning | 0 | 0.34 | 2011 |
Evaluation of deflection routing on various NoC topologies | 3 | 0.40 | 2011 |
Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks | 2 | 0.39 | 2011 |
Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems | 1 | 0.35 | 2011 |
3-D integration and the limits of silicon computation. | 0 | 0.34 | 2011 |
Cooperative Communication Based Barrier Synchronization In On-Chip Mesh Architectures | 3 | 0.46 | 2011 |
Realization and performance comparison of sequential and weak memory consistency models in network-on-chip based multi-core systems | 3 | 0.41 | 2011 |