Name
Abstract | ||
|---|---|---|
This paper presents a new model for gate-to-channel GOS defects. The transistors used in digital cell library are usually designed with a minimum-size. This new model permits to handle minimal-length transistors allowing the simulation of GOS defects ... |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1023/A:1024691909923 | J. Electronic Testing |
Keywords | Field | DocType |
system-chips,IEEE-1149.1,multi-TAP,software-debug,design-for-debug | Architecture,Computer science,Debugger,Field-programmable gate array,Chip,Real-time computing,Software,Embedded system,Controller architecture | Journal |
Volume | Issue | ISSN |
19 | 4 | 1573-0727 |
Citations | PageRank | References |
1 | 0.52 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bart Vermeulen | 1 | 142 | 13.81 |
| Tom Waayers | 2 | 128 | 11.47 |
| Sjaak Bakker | 3 | 19 | 2.69 |