Name
Abstract | ||
|---|---|---|
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems because of their dynamic and adaptive behavior, and thus need special attention to be used in hard real-time systems. A lot of progress has been achieved in the last ten years to statically predict worst-case execution times (WCETs) of tasks on architectures with caches. However, cache-aware WCET analysis techniques are not always applicable due to the lack of documentation of hardware manuals concerning the cache replacement policies. Moreover, they tend to be pessimistic with some cache replacement policies (e.g. random replacement policies) [6]. Lastly, caches are sources of timing anomalies in dynamically scheduled processors [13] (a cache miss may in some cases result in a shorter execution time than a hit). To reconciliate performance and predictability of caches, we propose in this paper algorithms for software control of instruction caches. The proposed algorithms statically divide the code of tasks into regions, for which the cache contents is statically selected. At run-time, at every transition between regions, the cache contents computed off-line is loaded into the cache and the cache replacement policy is disabled (the cache is locked). Experimental results provided in the paper show that with an appropriate selection of regions and cache contents, the worst-case performance of applications with locked instruction caches is competitive with the worst-case performance of unlocked caches. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ECRTS.2006.32 | ECRTS |
Keywords | Field | DocType |
paper show,cache memory,cache content,random replacement policy,wcet-centric software-controlled instruction caches,worst-case execution time,worst-case performance,cache replacement policy,locked instruction cache,hard real-time systems,paper algorithm,instruction cache,worst case execution time,adaptive behavior,scheduling,computational complexity,real time systems | Cache invalidation,Cache pollution,Cache,Computer science,Parallel computing,Real-time computing,Page cache,Cache algorithms,Cache coloring,Bus sniffing,Smart Cache | Conference |
ISSN | ISBN | Citations |
1068-3070 | 0-7695-2619-5 | 50 |
PageRank | References | Authors |
2.31 | 20 | 1 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Isabelle Puaut | 1 | 1708 | 89.84 |