Name
Title | ||
|---|---|---|
Local transformation techniques for multi-level logic circuits utilizing circuit symmetries for power reduction |
Abstract | ||
|---|---|---|
In this paper, we present several optimization techniques for power reduction utilizing circuit symmetries. There are four kinds of symmetries that we detect in a given circuit implementation. First, we propose an algorithm for detecting the four different types of symmetries in a given circuit implementation of a Boolean function. Several re-synthesis techniques utilizing such symmetries are proposed. These techniques enable us to optimize power consumption and delay with no (or very little) area overhead. We have carried out experiments on MCNC benchmark circuits to demonstrate the efficiency of the proposed techniques. The average power reduction is 14% with little or no area and/or delay overhead. |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1145/280756.280904 | Monterey, CA, USA |
Keywords | Field | DocType |
circuit symmetries,delay,aver age power reduction,local transformation technique,power consumption,logic cad,local transformation techniques,ar ea overhead,ar ea,delay overhead,boolean function,optimization techniques,circuit optimisation,low-power electronics,multi-level logic circuits,ose dtechniques,delays,vlsi,multivalued logic circuits,integrated circuit design,multi-level logic circuit,circuit implementation,power reduction,mcnc benchmark circuit,circuit symmetry,boolean functions,mcnc benchmark circuits,low power electronics,power,fpgas,embedded | Boolean function,Logic gate,Computer science,Field-programmable gate array,Electronic engineering,Integrated circuit design,Electronic circuit,Very-large-scale integration,Homogeneous space,Low-power electronics | Conference |
ISBN | Citations | PageRank |
1-58113-059-7 | 6 | 0.52 |
References | Authors | |
18 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ki-seok Chung | 1 | 189 | 18.76 |
| C. L. Liu | 2 | 6191 | 970.79 |