Title
FPGA implementation of a novel architecture for performance enhancement of Radix-2 FFT
Abstract
This paper presents a novel architecture for the enhancement of performance of compute intensive Fast Fourier Transform (FFT) algorithm which is common in many signal processing applications. The proposed architecture exhibits faster response time compared to radix-2 'Single-path Delay Feedback (SDF)' architecture and 'radix-2 Multi-path Delay Commutator (MDC)' architecture. The architecture was simulated using Modelsim and was implemented on Xilinx Virtex 4 FPGA.
Year
DOI
Venue
2012
10.1145/2234336.2234341
SIGARCH Computer Architecture News
Keywords
Field
DocType
novel architecture,signal processing application,intensive fast fourier transform,performance enhancement,xilinx virtex,radix-2 fft,single-path delay feedback,faster response time,radix-2 multi-path delay commutator,fpga implementation,proposed architecture,dft,fast fourier transform,signal processing,fft
Signal processing,ModelSim,Architecture,Computer architecture,Computer science,Parallel computing,Field-programmable gate array,Response time,Radix,Fast Fourier transform,Virtex
Journal
Volume
Issue
Citations 
40
2
0
PageRank 
References 
Authors
0.34
8
2
Name
Order
Citations
PageRank
Nishant Kumar Giri140.87
Amitabha Sinha2147.00