Name
Abstract | ||
|---|---|---|
With the rapid progress in semiconductor technologies, more and more accelerators can be integrated onto a single SoC chip. In SoCs, accelerators often require deterministic data access. However, as more and more applications are running simultaneous, latency can vary significantly due to contention. To address this problem, we propose a template-based memory access engine (MAE) for accelerators in SoCs. The proposed MAE can handle several common memory access patterns observed for near-future accelerators. Our evaluation results show that the proposed MAE can significantly reduce memory access latency and jitter, thus very effective for accelerators in SoCs.
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Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ASPDAC.2011.5722175 | ASP-DAC |
Keywords | Field | DocType |
proposed mae,single soc chip,template-based memory access engine,evaluation result,near-future accelerator,rapid progress,memory access latency,semiconductor technology,deterministic data access,common memory access pattern,jitter,system on a chip,system on chip,chip,memory management,data access | Power management,System on a chip,Computer science,Latency (engineering),Chip,Memory management,Jitter,Data access,Domino circuit,Embedded system | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4244-7516-2 | 5 |
PageRank | References | Authors |
0.44 | 14 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Bin Li | 1 | 208 | 8.64 |
| Zhen Fang | 2 | 91 | 7.62 |
| Ravishankar K. Iyer | 3 | 1119 | 75.72 |