Paper Info
Title
A power and temperature aware DRAM architecture
Abstract
Technological advances enable modern processors to utilize increasingly larger DRAMs with rising access frequencies. This is leading to high power consumption and operating temperature in DRAM chips. As a result, temperature management has become a real and pressing issue in high performance DRAM systems. Traditional low power techniques are not suitable for high performance DRAM systems with high bandwidth. In this paper, we propose and evaluate a customized DRAM low power technique based on page hit aware write buffer (PHA-WB). Our proposed approach reduces DRAM system power consumption and temperature without any performance penalty. Our experiments show that a system with a 64-entry PHA-WB could reduce the total DRAM power consumption by up to 22.0% (9.6% on average). The peak and average temperature reductions are 6.1degC and 2.1degC, respectively.
Year
DOI
Venue
2008
10.1145/1391469.1391691
DAC
Keywords
Field
DocType
high bandwidth,high power consumption,dram architecture,low power technique,page hit aware write buffer,traditional low power technique,high performance dram system,temperature aware dram architecture,dram chip,buffer storage,low-power electronics,thermal management (packaging),dram chips,dram power consumption,dram system power consumption,dram,average temperature reduction,customized dram low power,total dram power consumption,memory architecture,power,temperature management,temperature,energy management,chip,computer architecture,system performance,memory management,bandwidth,low power electronics
Dram,Operating temperature,Energy management,Computer science,Real-time computing,Write buffer,Bandwidth (signal processing),Energy consumption,Memory architecture,Low-power electronics,Embedded system
Conference
ISSN
ISBN
Citations 
0738-100X
978-1-60558-115-6
11
PageRank 
References 
Authors
0.71
6
4
Name
Order
Citations
PageRank
Song Liu12168.86
Seda Öǧrenci Memik248842.57
Yu Zhang32208.72
Gokhan Memik41694111.88