Name
Abstract | ||
|---|---|---|
This paper presents an experiment which aims to assess the potential impact on performance yielded by augmenting a TriMedia/CPU64 processor with a reconfigurable core. We first propose the skeleton of an extension of theTri-Media/CPU64 architecture, which consists of a Reconfigurable Functional Unit (RFU) and the associated instructions. Then, we address the computation of the 8脳8 IDCT on such extended TriMedia and propose a scheme to implement the 1-D IDCT operation on the RFU. When implemented on an ACEX EP1K100 FPGA from Altera, the proposed 1-D IDCT exhibits a latency of 16 and a recovery of 2 TriMedia (200 MHz) cycles, and occupies 42% of the device. By configuring the 1-D IDCT computing facility on the RFU at application load-time, a 2-D IDCT including all overheads can be computed with the throughput of 1/32 IDCT/cycle. This is an improvement of more than 40% over the standard TriMedia/CPU64. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/FCCM.2001.9 | Rohnert Park, CA, USA |
Keywords | Field | DocType |
1-d idct operation,application load-time,standard trimedia,extended trimedia,proposed 1-d idct,fpga-augmented trimedia,2-d idct,reconfigurable functional unit,1-d idct computing facility,idct implementation,cpu64 architecture,cpu64 processor,skeleton,computer architecture,scheduling algorithm,computer applications,throughput,field programmable gate arrays | Computer architecture,Computer science,Scheduling (computing),Parallel computing,Field-programmable gate array,Real-time computing,Throughput,Processor scheduling,Discrete cosine transforms,TriMedia,Embedded system | Conference |
ISBN | Citations | PageRank |
0-7695-2667-5 | 14 | 1.00 |
References | Authors | |
12 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mihai Sima | 1 | 95 | 16.66 |
| Sorin Cotofana | 2 | 245 | 39.03 |
| Jos T. J. van Eijndhoven | 3 | 135 | 16.27 |
| Stamatis Vassiliadis | 4 | 2007 | 227.06 |
| Kees Vissers | 5 | 14 | 1.00 |