Paper Info
Title
Performance evaluation of on-chip interconnect IP using CBR traffic generator model
Abstract
The communication efficiency plays a crucial role in achieving high system performance in many multimedia SoCs (System-On-Chips). Increased requirements on high bandwidth on-chip communication have led to the emergence of complicated communication architectures and algorithms. However, without thorough analysis of bandwidth requirements of applications, we tend to over-provision resources to avoid potential performance degradation. In this paper, we present a CBR-based traffic modeling technique along with a performance evaluation framework. By using this evaluation technique, we can estimate the sustained performance of on-chip communication infrastructure used in multimedia SoCs. The traffic behaviors of a multimedia application have been captured and analyzed to characterize individual operations which are modeled using traffic generators to replace hardware IPs in evaluation process. The simulation results show that this approach is also effective in discovering the peak performance of on-chip network and bandwidth allocation to IPs.
Year
DOI
Venue
2009
10.1145/1644993.1645111
ICHIT
Keywords
Field
DocType
complicated communication architecture,performance evaluation framework,communication efficiency,multimedia socs,high system performance,cbr traffic generator model,high bandwidth on-chip communication,potential performance degradation,sustained performance,on-chip communication infrastructure,peak performance,chip,system performance,system on chip,traffic generator,bandwidth allocation,simulation
Traffic generation model,Bandwidth allocation,Computer science,Computer network,Bandwidth (signal processing),Interconnection,Embedded system,High bandwidth
Conference
Citations 
PageRank 
References 
0
0.34
1
Authors
5
Name
Order
Citations
PageRank
Kee Beom Kim100.68
Seong Min Jo200.68
Jin Woo Song351.89
Ki-seok Chung418918.76
Yong Ho Song519923.33