Name
Abstract | ||
|---|---|---|
Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. For CAD tools, this situation increases the difficulty of successfully mapping a circuit into the low-cost FPGAs. Instead of switching to resource-rich FPGAs, the designers could employ depopulation-based clustering techniques which underuse CLBs, hence improve routability by spreading the logic over the architecture. However, all depopulation-based clustering algorithms to this date increase critical path delay. In this paper, we present a timing-driven nonuniform depopulation-based clustering technique, T-NDPack, that targets critical path delay and channel width constraints simultaneously. T-NDPack adjusts the CLB capacity based on the criticality of the Basic Logic Element (BLE). Results show that T-NDPack reduces minimum channel width by 11.07% while increasing the number of CLBs by 13.28% compared to T-VPack. More importantly, T-NDPack decreases critical path delay by 2.89%. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1155/2010/158602 | Int. J. Reconfig. Comp. |
Keywords | DocType | Volume |
basic logic element,low-cost fpgas,targets critical path delay,depopulation-based clustering algorithm,date increase critical path,configurable logic blocks,critical path delay,underuse clbs,clustering technique,comparable number,timing-driven nonuniform | Journal | 2010, |
Citations | PageRank | References |
6 | 0.47 | 14 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hanyu Liu | 1 | 6 | 0.47 |
| Ali Akoglu | 2 | 157 | 29.40 |