Paper Info
Title
Low latency and power efficient VD using register exchanged state-mapping algorithm
Abstract
In this paper, a new implementation of the Viterbi decoder is proposed. RE state-mapping algorithm combines TB algorithm with the RE algorithm. By updating the starting point of the state for each memory bank, the trace back operation can be eliminated. This result reduces the latency of the TB algorithm and the resource usage of RE algorithm. When the memory unit is 3, the resource usage is 6306 bits and the latency is 72 clocks. The resource usage is 74% smaller than the RE algorithm, and the latency is 34% smaller than the k-pointer even TB algorithm. The power consumption of each algorithm are also analyzed and compared. Because the resource usage is directly related to the power, the power consumption of this scheme is also reduced as stated in D. Liu and C. Svensson (1994). Actually, the estimated power consumption is about 12% smaller than the RE algorithm.
Year
DOI
Venue
2005
10.1109/IWSOC.2005.81
IWSOC
Keywords
Field
DocType
maximum likelihood decoding,latency reduction,power consumption,low latency,power efficient vd,estimated power consumption,trace back operation,memory bank,viterbi decoding,resource allocation,viterbi decoder,resource usage,register exchanged state-mapping algorithm,state-mapping algorithm,new implementation,tb algorithm,memory unit,cost function,convergence,viterbi algorithm,algorithm design and analysis,power efficiency,writing
Memory bank,Sequential decoding,Soft output Viterbi algorithm,Computer science,Latency (engineering),Parallel computing,Real-time computing,Viterbi decoder,Resource allocation,Latency (engineering),Iterative Viterbi decoding
Conference
ISBN
Citations 
PageRank 
0-7695-2403-6
0
0.34
References 
Authors
4
2
Name
Order
Citations
PageRank
Sang-Ho Seo132.54
Sin-Chong Park28022.58