Paper Info
Title
Designing BEE: a hardware emulation engine for signal processing in low-power wireless applications
Abstract
This paper describes the design of a large-scale emulation engine and an application example from the field of low-power wireless devices. The primary goal of the emulator is to support design space exploration of real-time algorithms. The emulator is customized for dataflow dominant architectures, especially focusing on telecommunication-related applications. Due to its novel routing architecture and application-specific nature, the emulator is capable of real-time execution of a class of algorithms in its application space. Moreover, the dataflow structure facilitates the development of a highly abstracted design flow for the emulator. Simulations and practical measurements on commercial development boards are used to verify that real-time emulation of a low-power TDMA receiver is feasible at a clock speed of 25 MHz.
Year
DOI
Venue
2003
10.1155/S1110865703212154
EURASIP J. Adv. Sig. Proc.
Keywords
Field
DocType
application space,real-time algorithm,design space exploration,real-time emulation,design flow.,dataflow structure,low-power wireless application,signal processing,rapid prototyping,real-time execution,hardware emulation engine,commercial development board,hardware emulation,abstracted design flow,dataflow dominant architecture,designing bee,low-power,fpga,application example,real time,design flow
Wireless,Computer science,Field-programmable gate array,Design flow,Dataflow,Emulation,Design space exploration,Clock rate,Embedded system,Hardware emulation
Journal
Volume
Issue
ISSN
2003,
6
1687-6180
Citations 
PageRank 
References 
6
2.97
23
Authors
5
Name
Order
Citations
PageRank
Kimmo Kuusilinna121627.10
Chen Chang217426.12
M. Josephine Ammer383.56
Brian C. Richards47237.78
Robert W. Brodersen51857401.31