Name
Title | ||
|---|---|---|
A Digit-Serial Reconfigurable VLSI Based on Quaternary Inter-Cell Data Transfer Scheme. |
Abstract | ||
|---|---|---|
A high-throughput recontigurable VLSI using a digit-serial architecture is proposed, where two-bit data for each operand enters a cell per clock cycle. The interconnection complexity between two adjacent cells is reduced by using a quaternary inter-cell data transfer scheme. In a cell, the quaternary data is converted into binary dual-rail voltage signals, and hi nary-controlled current steering technique is introduced utilizing a programmable three-level differential-pair circuit to implement an arbitrary two-variable binary logic function and a full-adder sum/carry. In the cell output circuit, switched current sources are used to reduce power dissipation. Moreover, the CMOS logic is used to make driving capability of a ID flip-flop high. As a result, the maximum throughput of the proposed digit-serial reconfigurable VLSI using quaternary cells is twice that of the bit-serial reconfigurable VLSI, while the power-delay product is reduced to 74%. Dramatic improvement of the recontigurable VLSI can be achieved. |
Year | Venue | Keywords |
|---|---|---|
2012 | JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING | Digit-serial architecture,Fine-grain reconfigurable VLSI,Multiple-valued VLSI,High throughput,Multiple-valued source-coupled logic,MOS current-mode logic,Low power consumption |
Field | DocType | Volume |
Computer architecture,Data transmission,Computer science,Parallel computing,Numerical digit,Very-large-scale integration | Journal | 20 |
Issue | ISSN | Citations |
1-2 | 1542-3980 | 15 |
PageRank | References | Authors |
0.58 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xu Bai | 1 | 37 | 9.94 |
| Nobuaki Okada | 2 | 38 | 3.86 |
| Michitaka Kameyama | 3 | 431 | 99.93 |