Title
Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems
Abstract
The great variety of pixel dynamics of real-time video-processing systems (RTVPS), ranging from color, grayscale, or binary pixels, means that a careful design and specification of bit widths is required. It is obvious that the bit-width specification will affect the total memory storage requirement. However, what is not so obvious is that the bit-width specification will also affect the design of the memory hierarchy, an impact similar for both hardware and software implementations. We have developed an integer-nonlinear-program formulation for the optimization of the memory hierarchy of RTVPS. An active surveillance video camera is introduced as a test case. We demonstrate how the optimization model can reduce the on-chip memory storage by 61% compared to a nonoptimal memory hierarchy
Year
DOI
Venue
2007
10.1109/TCAD.2006.884569
IEEE Trans. on CAD of Integrated Circuits and Systems
Keywords
DocType
Volume
on-chip memory storage,active surveillance video camera,total memory storage requirement,Bit-Width Constrained Memory,optimization model,Real-Time Video Systems,memory hierarchy,bit width,bit-width specification,nonoptimal memory hierarchy,binary pixel,careful design,Hierarchy Optimization
Journal
26
Issue
ISSN
Citations 
4
0278-0070
1
PageRank 
References 
Authors
0.36
15
7
Name
Order
Citations
PageRank
Benny Thörnberg1318.44
Martin Palkovic221316.11
Qubo Hu3202.11
Leif Olsson463.40
P. G. Kjeldsberg525313.54
M. O'Nils610.36
F. Catthoor789783.95