| Adaptive Mapping and Parameter Selection Scheme to Improve Automatic Code Generation for GPUs | 0 | 0.34 | 2014 |
| Fast multidimension multichoice knapsack heuristic for MP-SoC runtime management | 24 | 0.95 | 2011 |
| Ultra low energy Domain Specific Instruction-set Processor for on-line surveillance | 2 | 0.40 | 2010 |
| Energy-performance Exploration of a CGA-based SDR Processor | 8 | 0.67 | 2009 |
| Performance Analysis of Slotted Carrier Sense IEEE 802.15.4 Medium Access Layer | 78 | 3.82 | 2008 |
| Storage Estimation and Design Space Exploration Methodologies for the Memory Management of Signal Processing Applications | 6 | 0.47 | 2008 |
| How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design | 0 | 0.34 | 2008 |
| Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems | 1 | 0.36 | 2007 |
| Incremental hierarchical memory size estimation for steering of loop transformations | 9 | 0.67 | 2007 |
| Fast memory footprint estimation based on maximal dependency vector calculation | 4 | 0.41 | 2007 |
| Yield prediction for architecture exploration in nanometer technology nodes:: a model and case study for memory organizations | 3 | 0.45 | 2006 |
| Loop Transformation Methodologies for Array-Oriented Memory Management | 4 | 0.49 | 2006 |
| A combined DMA and application-specific prefetching approach for tackling the memory latency bottleneck | 17 | 0.72 | 2006 |
| Eliminating CPU overhead for on-the-fly content adaptation with MPEG-4 wavelet subdivision surfaces | 5 | 0.61 | 2006 |
| System-level process variability compensation on memory organizations of dynamic applications: a case study | 8 | 0.59 | 2006 |
| Improving superword level parallelism support in modern compilers | 9 | 0.72 | 2005 |
| Mapping the MPEG-4 visual texture decoder: a system-level design technique based on heterogeneous platforms | 2 | 0.39 | 2005 |
| A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications | 14 | 0.82 | 2005 |
| Energy Efficient Memory Architecture for High Speed Decoding of Block Turbo-Codes with the Fang-Buda Algorithm | 0 | 0.34 | 2005 |
| Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications | 15 | 0.68 | 2005 |
| A Complete Network-On-Chip Emulation Framework | 59 | 3.13 | 2005 |
| Object-Distribution Analysis for Program Decomposition and Re-Clustering | 1 | 0.36 | 2005 |
| Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs | 25 | 1.36 | 2005 |
| Optimizing the Memory Bandwidth with Loop Morphing | 4 | 0.42 | 2004 |
| Storage requirement estimation for optimized design of data intensive applications | 13 | 0.58 | 2004 |
| Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors | 1 | 0.39 | 2004 |
| SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms | 7 | 0.67 | 2003 |
| A scalable MPEG-4 wavelet-based visual texture compression system with optimized memory organization | 2 | 0.37 | 2003 |
| Memory Power Reduction for High-Speed Implementation of Turbo Codes | 1 | 0.41 | 2003 |
| Estimating influence of data layout optimizations on SDRAM energy consumption | 7 | 0.61 | 2003 |
| Systematic Application of Data Transfer and Storage Optimizing Code Transformations for Power Consumption and Execution Time Reduction in ACROPOLIS: A Pre-Compiler for Multimedia Applications | 1 | 0.35 | 2003 |
| Global interconnect trade-off for technology over memory modules to application level: case study | 9 | 0.75 | 2003 |
| Data Reuse Exploration Techniques for Loop-Dominated Applications | 21 | 1.11 | 2002 |
| System-level exploration of association table implementations in telecom network applications | 2 | 0.43 | 2002 |
| System-level performance optimization of the data queueing memory management in high-speed network processors | 11 | 1.00 | 2002 |
| Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder | 8 | 0.51 | 2002 |
| Interconnect exploration for future wire dominated technologies | 0 | 0.34 | 2002 |
| Dynamic memory management methodology applied to embedded telecom network systems | 2 | 0.54 | 2002 |
| Systematic power-performance trade-off in MPEG-4 by means of selective function inlining steered by address optimisation opportunities | 2 | 0.38 | 2002 |
| Analyzing energy friendly steady state phases of dynamic application execution in terms of sparse data structures | 4 | 0.53 | 2002 |
| Multi-objective abstract data type refinement for mapping tables in telecom network applications | 2 | 0.52 | 2002 |
| Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications | 6 | 0.58 | 2001 |
| Data and memory optimization techniques for embedded systems | 211 | 9.47 | 2001 |
| Cache conscious data layout organization for embedded multimedia applications | 20 | 1.92 | 2001 |
| Task concurrency management methodology summary | 2 | 0.42 | 2001 |
| The Local Wavelet Transform: a memory-efficient, high-speed architecture optimized to a Region-Oriented Zero-Tree coder | 15 | 0.97 | 2000 |
| Extended design reuse trade-offs in hardware-software architecture mapping | 0 | 0.34 | 2000 |
| Analysis of high-level address code transformations for programmable processors | 25 | 1.18 | 2000 |
| A Specification Refinement Methodology for Power Efficient Partitioning of Data-Dominated Algorithms Within Performance Constraints | 1 | 0.36 | 2000 |
| System-Level Energy-Delay Exploration for Multimedia Applications on Embedded Cores with Hardware Cache | 3 | 0.50 | 1999 |
