Name
Title | ||
|---|---|---|
Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates |
Abstract | ||
|---|---|---|
This work presents a fault-tolerant IC version of a mass-produced 8-bit microprocessor from the M68HC11 family. It is able to tolerate Single Event Transients (SETs) and Single Event Upsets (SEUs). Based on the Triple Modular Redundancy (TMR) and Time Redundancy (TR) fault tolerance techniques, a protection scheme was designed and implemented at high level in the target microprocessor by using only standard logic gates. A typical IC design flow was developed by means of commercial CAD tools. Functional testing and fault injection simulations through benchmark executions were performed as a design verification testing. Furthermore, fault-tolerant IC design issues and results in area, performance and power were compared with a non-protected microprocessor version. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1145/1150343.1150394 | SBCCI |
Keywords | Field | DocType |
8-bit microprocessor,single event transients,design verification testing,time redundancy,typical ic design flow,non-protected microprocessor version,single event upsets,standard gate,soft error,high level,target microprocessor,fault-tolerant ic version,fault-tolerant ic design issue,design flow,fault tolerant,functional testing,logic gate | Computer science,Microprocessor,8-bit,Triple modular redundancy,Real-time computing,Integrated circuit design,Fault tolerance,Redundancy (engineering),Fault injection,Embedded system,Software verification | Conference |
ISBN | Citations | PageRank |
1-59593-479-0 | 1 | 0.35 |
References | Authors | |
6 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rodrigo Possamai Bastos | 1 | 80 | 13.80 |
| Fernanda Lima Kastensmidt | 2 | 554 | 61.82 |
| Ricardo Reis | 3 | 249 | 28.56 |