Name
Abstract | ||
|---|---|---|
Shared memory is a common interprocessor communication paradigm for single-chip multiprocessor platforms. Snoop-based cache coherence is a very successful technique that provides a clean shared-memory programming abstraction in general-purpose chip multiprocessors, but there is no consensus on its usage in resource-constrained multiprocessor systems on chips (MPSoCs) for embedded applications. This work aims at providing a comparative energy and performance analysis of cache-coherence support schemes in MPSoCs. Thanks to the use of a complete multiprocessor simulation platform, which relies on accurate technology-homogeneous power models, we were able to explore different cache-coherent shared-memory communication schemes for a number of cache configurations and workloads. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1145/1151074.1151081 | ACM Trans. Embedded Comput. Syst. |
Keywords | Field | DocType |
cache coherence,low power,accurate technology-homogeneous power model,shared-memory mpsocs,different cache-coherent shared-memory communication,cache configuration,complete multiprocessor simulation platform,shared memory,clean shared-memory programming abstraction,snoop-based cache coherence,system-on-chip,cache coherence tradeoffs,resource-constrained multiprocessor system,common interprocessor communication paradigm,multiprocessor,single-chip multiprocessor platform,system on chip | Computer architecture,System on a chip,Shared memory,Computer science,Cache,Parallel computing,MESI protocol,Chip,Multiprocessing,Real-time computing,Bus sniffing,Cache coherence | Journal |
Volume | Issue | Citations |
5 | 2 | 26 |
PageRank | References | Authors |
1.10 | 16 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mirko Loghi | 1 | 218 | 17.83 |
| Massimo Poncino | 2 | 460 | 57.48 |
| Luca Benini | 3 | 13116 | 1188.49 |