Name
Abstract | ||
|---|---|---|
We propose a low-overhead scan design methodology which employs a new test point insertion technique to establish scan paths through the functional logic. The technique re-uses the existing functional logic; as a result, the design-for-testability (DFT) overhead on area or timing can be minimized. In this paper we show an algorithm which considers the test point insertion for reducing the area overhead for the full scan design. We also discuss its application to timing-driven partial scan design |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/DAC.1996.545585 | DAC |
Keywords | Field | DocType |
scan paths,timing-driven partial scan design,logic cad,combinational circuits,test point insertion,low-overhead scan design methodology,circuit cad,integrated circuit design,design-for-testability,combinational logic,design for testability,functional logic,logic testing,multiplexing,automatic test pattern generation,design methodology,logic design,controllability | Design for testing,Logic synthesis,Permission,Automatic test pattern generation,Computer science,Scan chain,Combinational logic,Real-time computing,Electronic engineering,Integrated circuit design,Multiplexing | Conference |
ISSN | ISBN | Citations |
0738-100X | 0-7803-3294-6 | 5 |
PageRank | References | Authors |
0.63 | 10 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chih-chang Lin | 1 | 135 | 10.86 |
| Malgorzata Marek-Sadowska | 2 | 2272 | 213.72 |
| Kwang-Ting Cheng | 3 | 5755 | 513.90 |
| Mike Tien-Chien Lee | 4 | 443 | 71.04 |