A test synthesis approach to reducing BALLAST DFT overhead | 1 | 0.35 | 1997 |
Power analysis and minimization techniques for embedded DSP software | 106 | 12.40 | 1997 |
Domain–Specific High–Level Modeling and Synthesis for ATM Switch Prototyping | 0 | 0.34 | 1997 |
On the control-subroutine implementation of subprogram synthesis | 1 | 0.36 | 1997 |
Domain-specific high-level modeling and synthesis for ATM switch design using VHDL | 6 | 0.65 | 1996 |
Instruction level power analysis and optimization of software | 254 | 39.37 | 1996 |
Eliminating false loops caused by sharing in control path | 1 | 0.36 | 1996 |
Sequential Permissible Functions and their Application to Circuit Optimization | 1 | 0.40 | 1996 |
Using register-transfer paths in code generation for heterogeneous memory-register architectures | 31 | 3.19 | 1996 |
Test point insertion: scan paths through combinational logic | 5 | 0.63 | 1996 |
Cost-free scan: a low-overhead scan path design methodology | 14 | 1.16 | 1995 |
Power analysis and low-power scheduling techniques for embedded DSP software | 23 | 11.84 | 1995 |