Name
Abstract | ||
|---|---|---|
A 2.5-GHz 8-phase phase-locked loop (PLL) was proposed for 10 Gbps system on chip (SoC) transmission links application. The proposed self-calibration method can adjust the multi-band voltage control oscillator (VCO) to compensate for process, voltage and temperature (PVT) variations. The small KVCO can reduce the effect of power/ ground (P/G) and substrate noise. The PLL is implemented in 0.13 mum CMOS technology. The PLL output jitter is 18.55 ps (p-p) where the reference clock jitter is 20 ps (p-p). The total power dissipation is 21 mW at 2.5-GHz and the core area is 0.08 mm2. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ICECS.2008.4674971 | ICECS |
Keywords | Field | DocType |
multi-band voltage control oscillator,calibration,system on chip,jitter self-calibration pll,voltage-controlled oscillators,bit rate 10 gbit/s,jitter,power 21 mw,system-on-chip,phase locked loops,soc transmission links,phase-locked loop,frequency 2.5 ghz,phase locked loop,radiation detectors,noise,phase lock loop | Phase-locked loop,System on a chip,Computer science,Dissipation,Voltage,PLL multibit,CMOS,Control engineering,Voltage-controlled oscillator,Electronic engineering,Jitter | Conference |
ISBN | Citations | PageRank |
978-1-4244-2182-4 | 0 | 0.34 |
References | Authors | |
3 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kuo-hsing Cheng | 1 | 325 | 77.87 |
| Yu-Chang Tsai | 2 | 33 | 3.68 |
| Kai-Wei Hong | 3 | 17 | 3.34 |
| Yen-Hsueh Wu | 4 | 11 | 1.83 |