Yu-Chang Tsai - Citegraph

Author Info

Name	Affiliation	Papers
YU-CHANG TSAI	Natl Cent Univ, Dept Elect Engn, MSIC Lab, Jhongli 32001, Taoyuan County, Taiwan	5
Collaborators	Citations	PageRank
8	33	3.68
Referers	Referees	References
100	81	39

Publications (5 rows)

Collaborators (8 rows)

Referers (100 rows)

Referees (81 rows)

Title	Citations	PageRank	Year
A 0.5-V 0.4–2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip	22	1.51	2011
A CMOS adaptive equalizer using low-voltage zero generators technique	0	0.34	2010
A 5-Gb/s Inductorless CMOS Adaptive Equalizer for PCI Express Generation II Applications	11	1.15	2010
A Low Jitter Self-Calibration Pll For 10-Gbps Soc Transmission Links Application	0	0.34	2009
A low jitter self-calibration PLL for 10Gbps SoC transmission links application	0	0.34	2008

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