Name
Abstract | ||
|---|---|---|
A multi-GHz arbitrary timing generator (ATG) design is described and demonstrated in a hardware prototype. The objective of the ATG is to realize ATE hardware that nearly matches the unlimited timing flexibility of software simulation tools. The ATG allows timing edges to be programmed at almost any desired point within the test, with minimal constraints. The delay of every edge can be changed on a cycle-to-cycle basis. The period (frequency) can be changed on a bit-by-bit basis. Real-time algorithmic calculation of timing values is accomplished using a pipelined FPGA controller so that highly complex timing sequences can be synthesized. The ATG generates timing edges according to the FPGA calculations, and combines these with serialized digital “pattern” data to create the desired signal waveforms. A prototype supports ∼10ps resolution and achieves approximately +/−20ps accuracy (including 6σ random jitter). Its maximum sustainable data rate is 3.2Gbps (non-multiplexed) and 6.4Gbps (multiplexed). Bursts patterns up to 10.0Gbps are also demonstrated. Minimum pulse-width is ∼70ps. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TEST.2012.6401544 | ITC |
Keywords | DocType | Citations |
maximum sustainable data rate,cycle-to-cycle basis,hardware prototype,bit-by-bit basis,ATE hardware,timing value,data pattern serializer,multi-GHz arbitrary timing generator,unlimited timing flexibility,Multi-gigahertz arbitrary timing generator,FPGA calculation,complex timing sequence | Conference | 1 |
PageRank | References | Authors |
0.38 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Te-Hui Chen | 1 | 3 | 1.41 |
| Sung-Yeol Kim | 2 | 158 | 16.83 |
| Hosun Yoo | 3 | 8 | 1.51 |
| David C. Keezer | 4 | 68 | 17.00 |
| Hyun Woo Choi | 5 | 35 | 6.71 |
| Carl E. Gray | 6 | 1 | 0.38 |
| Seongkwan Lee | 7 | 1 | 0.38 |