Name
Abstract | ||
|---|---|---|
Nearly all platforms use a multi-layer memory hierarchy to bridge the enormous latency gap between the large off-chip memories and local register files. However, most of previous work on HW or SW controlled techniques for layer assignment have been mainly focussed on performance. As a result, the intermediate layers have been assigned too large sizes leading to energy inefficiency. In this paper we present a technique that takes advantage of both the temporal locality and limited lifetime of the arrays of the application for minimum energy consumption under layer size constraints. A prototype tool has been developed and tested using two real-life applications of industrial relevance. Following this approach we have been able to half the energy consumed by the memory hierarchy for each of our drivers. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/DATE.2003.1253746 | DATE |
Keywords | Field | DocType |
multi-layer memory hierarchy,large off-chip memory,layer size constraint,minimum energy consumption,layer assignment,memory hierarchy,intermediate layer,energy inefficiency,layer assignment echniques,multi-layered memory organisations,large size,low energy,enormous latency gap,memory latency,low power electronics,logic design,logic simulation,register file,carbon capture and storage,registers,energy efficiency,testing,chip,space exploration,hardware,application software | Locality of reference,Memory hierarchy,Efficient energy use,Computer science,Parallel computing,Real-time computing,Direct memory access,Application software,Energy consumption,CAS latency,Memory architecture | Conference |
ISBN | Citations | PageRank |
0-7695-1870-2 | 39 | 2.15 |
References | Authors | |
15 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| E. Brockmeyer | 1 | 321 | 16.32 |
| M. Miranda | 2 | 144 | 11.00 |
| H. Corporaal | 3 | 161 | 12.77 |
| F. Catthoor | 4 | 79 | 4.19 |