M. Miranda - Citegraph

Author Info

Name	Affiliation	Papers
M. MIRANDA	IMEC Lab., Leuven, Belgium	15
Collaborators	Citations	PageRank
47	144	11.00
Referers	Referees	References
299	226	132

Search Limit

100299

Publications (15 rows)

Collaborators (47 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Analysis of FinFET technology on memories	0	0.34	2012
New reliability mechanisms in memory design for sub-22nm technologies	1	0.36	2011
Variability aware modeling of SoCs: From device variations to manufactured system yield	13	0.58	2009
Yield prediction for architecture exploration in nanometer technology nodes:: a model and case study for memory organizations	3	0.45	2006
System-level process variability compensation on memory organizations of dynamic applications: a case study	8	0.59	2006
A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications	14	0.82	2005
Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications	15	0.68	2005
Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations	39	2.15	2003
Global interconnect trade-off for technology over memory modules to application level: case study	9	0.75	2003
Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder	8	0.51	2002
Interconnect exploration for future wire dominated technologies	0	0.34	2002
Systematic power-performance trade-off in MPEG-4 by means of selective function inlining steered by address optimisation opportunities	2	0.38	2002
Systematic speed-power memory data-layout exploration for cache controlled embedded multimedia applications	6	0.58	2001
Cache conscious data layout organization for embedded multimedia applications	20	1.92	2001
Architectural Exploration and Optimization for Counter Based Hardware Address Generation	6	0.54	1997

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